Re: Aufgaben und Übungen,

 0 0 0 0 0    1
 1 0 0 0 1    0
 2 0 0 1 0    1
 3 0 0 1 1    1
 4 0 1 0 0    0
 5 0 1 0 1    0
 6 0 1 1 0    1
 7 0 1 1 1    1
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    0
11 1 0 1 1    1
12 1 1 0 0    1
13 1 1 0 1    0
14 1 1 1 0    0
15 1 1 1 1    0


 0 0 0 0 0    1
 2 0 0 1 0    1
 3 0 0 1 1    1
 6 0 1 1 0    1
 7 0 1 1 1    1
 9 1 0 0 1    1
11 1 0 1 1    1
12 1 1 0 0    1


Gruppe 0:
 0 0 0 0 0    1
Gruppe 1:
 2 0 0 1 0    1
Gruppe 2:
 3 0 0 1 1    1
 6 0 1 1 0    1
 9 1 0 0 1    1
12 1 1 0 0    1
Gruppe 3:
 7 0 1 1 1    1
11 1 0 1 1    1


Gruppe 0:
 0 0 0 0 0    1
Gruppe 1:
 2 0 0 1 0    1
Gruppe 2:
 3 0 0 1 1    1
 6 0 1 1 0    1
 9 1 0 0 1    1
12 1 1 0 0    1
Gruppe 3:
 7 0 1 1 1    1
11 1 0 1 1    1

0;1     0 0 - 0
2;3     0 0 1 -
2;6     0 - 1 0
9;11    1 0 - 1
12      1 1 0 0
7       0 1 1 1

2;3     0 0 1 -
0;1     0 0 - 0
9;11    1 0 - 1
2;6     0 - 1 0
12      1 1 0 0
7       0 1 1 1

Minimale Rest"uberdeckung

        0   1   2   3   6   7   9   11  12
2;3             *   *
0;1     *   *
9;1         *                   *
2;6             *       *
12                                      *
7                           *


2;3     0 0 1 -
0;1     0 0 - 0
9;11    1 0 - 1
2;6     0 - 1 0
12      1 1 0 0
7       0 1 1 1

y <= (not x3 and not x2 and x1) or
    (not x3 and not x2 and not x0) or
    (x3 and not x2 and x0) or
    (not x3 and x1 and not x0) or
    (x3 and x2 and not x1 and not x0) or
    (not x3 and x2 and x1 and x0)

VHDL-Code

entity schaltnetz is
port
(
	x3, x2, x1, x0: in bit;
	y: out bit
);
end;

architecture verhalten of schaltnetz is
begin
	y <= (not x3 and not x2 and x1)
            or (not x3 and not x2 and not x0)
            or (x3 and not x2 and x0)
            or (not x3 and x1 and not x0)
            or (x3 and x2 and not x1 and not x0)
            or (not x3 and x2 and x1 and x0);
end;