0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 0 0 0 0 0 0 1 3 0 0 1 1 1 4 0 1 0 0 1 8 1 0 0 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 Gruppe 0: 0 0 0 0 0 1 Gruppe 1: 4 0 1 0 0 1 8 1 0 0 0 1 Gruppe 2: 3 0 0 1 1 1 12 1 1 0 0 1 Gruppe 3: 11 1 0 1 1 1 13 1 1 0 1 1 14 1 1 1 0 1 Gruppe 0: 0 0 0 0 0 1 Gruppe 1: 4 0 1 0 0 1 8 1 0 0 0 1 Gruppe 2: 3 0 0 1 1 1 12 1 1 0 0 1 Gruppe 3: 11 1 0 1 1 1 13 1 1 0 1 1 14 1 1 1 0 1 0:4 0 - 0 0 0:8 - 0 0 0 4:12 - 1 0 0 8:12 1 - 0 0 3:11 - 0 1 1 12:13 1 1 0 - 12:14 1 1 - 0 3:11 - 0 1 1 0:8 - 0 0 0 4:12 - 1 0 0 0:4 0 - 0 0 8:12 1 - 0 0 12:14 1 1 - 0 12:13 1 1 0 - Gruppe 2: 3:11 - 0 1 1 Gruppe 0: 0:8 - 0 0 0 Gruppe 1: 4:12 - 1 0 0 0:8:4:12 - - 0 0 Gruppe 0: 0:4 0 - 0 0 Gruppe 1: 8:12 1 - 0 0 12:14 1 1 - 0 12:13 1 1 0 - 3:11 - 0 1 1 0:8:4:12 - - 0 0 12:14 1 1 - 0 12:13 1 1 0 - 0 3 4 8 11 12 13 14 3:11 * * 0:8:4:12 * * * * 12:14 * * 12:13 * *
entity meinschaltnetz0010 is port ( x3, x2, x1, x0: in bit; y: out bit ) end; architecture verhalten of meinschaltnetz0010 is begin y <= (not x2 and x1 and x0) (not x1 and not x0) (x3 and x2 and not x0) (x3 and x2 and not x1) end;