b a x b a y 0 0 0 0 1 1 1 1 0 0 1 1 0 1 2 0 1 0 0 0 1 3 0 1 1 1 1 0 4 1 0 0 0 0 1 5 1 0 1 1 0 0 6 1 1 0 1 1 1 7 1 1 1 1 0 1 b a x b 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 1 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x a 0 0 0 0 1 1 0 0 1 0 2 0 1 0 0 3 0 1 1 1 4 1 0 0 0 5 1 0 1 0 6 1 1 0 1 7 1 1 1 0 b a x y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 1 5 1 0 1 0 6 1 1 0 1 7 1 1 1 1 b a x b 0 0 0 0 1 1 0 0 1 1 3 0 1 1 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x a 0 0 0 0 1 3 0 1 1 1 6 1 1 0 1 b a x y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 1 4 1 0 0 1 6 1 1 0 1 7 1 1 1 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 b a x a Gruppe 0: 0 0 0 0 1 Gruppe 1: 3 0 1 1 1 6 1 1 0 1 b a x y Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 2 0 1 0 1 4 1 0 0 1 Gruppe 2: 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 b a x b Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 0:1 0 0 - 1:3 0 - 1 1:5 - 0 1 3:7 - 1 1 5:7 1 - 1 6:7 1 1 - 0:1 0 0 - 6:7 1 1 - 1:3 0 - 1 5:7 1 - 1 1:5 - 0 1 3:7 - 1 1 1:3:5:7 - - 1 b := (not b and not a) or (b and a) or (x) b a x a Gruppe 0: 0 0 0 0 1 Gruppe 2: 3 0 1 1 1 6 1 1 0 1 a := (not b and not a and not x) or (not b and a and x) or (b and a and not x) b a x y Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 2 0 1 0 1 4 1 0 0 1 Gruppe 2: 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 0:1 0 0 - 0:2 0 - 0 0:4 - 0 0 2:6 - 1 0 4:6 1 - 0 6:7 1 1 - 0:1 0 0 - 6:7 1 1 - 0:2 0 - 0 4:6 1 - 0 0:4 - 0 0 2:6 - 1 0 y := (not b and not a) or (b and a) or (not x) b := (not b and not a) or (b and a) or (x) a := (not b and not a and not x) or (not b and a and x) or (b and a and not x) y := (not b and not a) or (b and a) or (not x)
entitity meinuebergangsschaltnetz is port ( b: inout bit; a: inout bit; x: in bit ); end; entity meinausgangsschaltnetz is port ( b: in bit; a: in bit; y: out bit; x: in bit ); end; architecture verhalten of meinuebergangsschaltnetz is begin b <= (not b and not a) or (b and a) or (x); a <= (not b and not a and not x) or (not b and a and x) or (b and a and not x); end; architecture verhalten of meinausgangsschaltnetz is begin y <= (not b and not a) or (b and a) or (not x); end: