b a x b a y 0 0 0 0 0 1 1 1 0 0 1 1 1 1 2 0 1 0 0 0 0 3 0 1 1 0 1 0 4 1 0 0 0 0 0 5 1 0 1 0 1 0 6 1 1 0 0 0 1 7 1 1 1 1 0 0 b a x b 0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 b a x a 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 1 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 0 b a x y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 1 7 1 1 1 0 b a x b 1 0 0 1 1 7 1 1 1 1 b a x a 0 0 0 0 1 1 0 0 1 1 3 0 1 1 1 5 1 0 1 1 b a x y 0 0 0 0 1 1 0 0 1 1 6 1 1 0 1 b a x b Gruppe 1: 1 0 0 1 1 Gruppe 3: 7 1 1 1 1 b a x a Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 b a x y Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 6 1 1 0 1 b a x b Gruppe 1: 1 0 0 1 1 Gruppe 3: 7 1 1 1 1 b <= (not b and not a and x) or (b and a and x) b a x a Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 0:1 0 0 - 1:3 0 - 1 1:5 - 0 1 a <= (not b and not a) or (not b and x) or (not a and x) b a x y Gruppe 0: 0 0 0 0 1 Gruppe 1: 1 0 0 1 1 Gruppe 2: 6 1 1 0 1 0:1 0 0 - 6 1 1 0 y <= (not b and not a) or (b and a and not x) b <= (not b and not a and x) or (b and a and x) a <= (not b and not a) or (not b and x) or (not a and x) y <= (not b and not a) or (b and a and not x)
entity meinausgangsschaltnetz is port ( a, b: in bit; y: out bit ); end; entity meinuebergangsschaltnetz is port ( a, b: inout bit; x: in bit ); end; architecture verhalten of meinausgangsschaltnetz is begin y <= (not b and not a) or (b and a and not x) end; architecture verhalten of meinuebergangsschaltnetz is begin b <= (not b and not a and x) or (b and a and x) a <= (not b and not a) or (not b and x) or (not a and x) end;