b a x b a y 0 0 0 0 0 0 1 1 0 0 1 1 0 1 2 0 1 0 0 1 1 3 0 1 1 0 0 1 4 1 0 0 1 1 1 5 1 0 1 0 0 1 6 1 1 0 0 1 1 7 1 1 1 1 1 1 b a x b 0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 b a x a 0 0 0 0 0 1 0 0 1 0 2 0 1 0 1 3 0 1 1 0 4 1 0 0 1 5 1 0 1 0 6 1 1 0 1 7 1 1 1 1 b a x y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x b 1 0 0 1 1 4 1 0 0 1 7 1 1 1 1 b a x a 2 0 1 0 1 4 1 0 0 1 6 1 1 0 1 7 1 1 1 1 b a x y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x b Gruppe 1: 1 0 0 1 1 4 1 0 0 1 Gruppe 3: 7 1 1 1 1 b <= (not b and not a and x) or (b and not a and not x) or (b and a and x) b a x a Gruppe 1: 2 0 1 0 1 4 1 0 0 1 Gruppe 2: 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 0:6 - 1 0 1:4 1 - 0 6:7 1 1 - a <= (a and not x) or (b and not x) or (b and a) b a x y 0 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 y <= 1 b <= (not b and not a and x) or (b and not a and not x) or (b and a and x) a <= (a and not x) or (b and not x) or (b and a) y <= 1
entitity meinausgangsschaltnetz is port ( a, b, x: in bit; y: out bit ); end; entitiy meinuebergangsschaltnetz is port ( a, b: inout bit; x: in bit; ); end; architecture verhalten of meinausgangsschaltnetz is begin y <= 1 end; architecture verhalten of meinuebergangsschaltnetz is begin b <= (not b and not a and x) or (b and not a and not x) or (b and a and x) a <= (a and not x) or (b and not x) or (b and a) end;