0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 Gruppe 1: 2 0 0 1 0 1 4 0 1 0 0 1 Gruppe 2: 3 0 0 1 1 1 5 0 1 0 1 1 6 0 1 1 0 1 Gruppe 3: 13 1 1 0 1 1 14 1 1 1 0 1 Gruppe 4: 15 1 1 1 1 1 Gruppe 1: 2 0 0 1 0 1 4 0 1 0 0 1 Gruppe 2: 3 0 0 1 1 1 5 0 1 0 1 1 6 0 1 1 0 1 Gruppe 3: 13 1 1 0 1 1 14 1 1 1 0 1 Gruppe 4: 15 1 1 1 1 1 2:3 0 0 1 - 2:6 0 - 1 0 4:5 0 1 0 - 4:6 0 1 - 0 5:13 - 1 0 1 6:13 - 1 1 0 13:15 1 1 - 1 14:15 1 1 1 - 2:3 0 0 1 - 4:5 0 1 0 - 14:15 1 1 1 - 4:6 0 1 - 0 13:15 1 1 - 1 2:6 0 - 1 0 5:13 - 1 0 1 6:13 - 1 1 0 Gruppe 1: 2:3 0 0 1 - 4:5 0 1 0 - Gruppe 3: 14:15 1 1 1 - Gruppe 1: 4:6 0 1 - 0 Gruppe 3: 13:15 1 1 - 1 2:6 0 - 1 0 Gruppe 2: 5:13 - 1 0 1 6:13 - 1 1 0 No Solution more! 2:3 0 0 1 - 4:5 0 1 0 - 14:15 1 1 1 - 4:6 0 1 - 0 13:15 1 1 - 1 2:6 0 - 1 0 5:13 - 1 0 1 6:13 - 1 1 0 y <= (not x3 and not x2 and x1) or (not x3 and x and not x1) or (x3 and x2 and x1) or (not x3 and x2 and not x0) or (x3 and x2 and x0) or (not x3 and x1 and not x0) or (x2 and not x1 and x0) or (x2 and x1 and not x0)
entity meinschaltnetz is port ( x3, x2, x1, x0: in bit; y: out bit ); end; architecture verhalten of meinschaltnetz is begin y <= (not x3 and not x2 and x1) or (not x3 and x and not x1) or (x3 and x2 and x1) or (not x3 and x2 and not x0) or (x3 and x2 and x0) or (not x3 and x1 and not x0) or (x2 and not x1 and x0) or (x2 and x1 and not x0) end;