b a x b a y 0 0 0 0 0 0 1 1 0 0 1 1 0 0 2 0 1 0 1 1 0 3 0 1 1 0 1 0 4 1 0 0 1 0 1 5 1 0 1 0 1 1 6 1 1 0 0 0 1 7 1 1 1 0 1 1 b a x b 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 1 5 1 0 1 0 6 1 1 0 0 7 1 1 1 0 b a x a 0 0 0 0 0 1 0 0 1 0 2 0 1 0 1 3 0 1 1 1 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1 b a x y 0 0 0 0 1 1 0 0 1 0 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x b 1 0 0 1 1 2 0 1 0 1 4 1 0 0 1 b a x a 2 0 1 0 1 3 0 1 1 1 5 1 0 1 1 7 1 1 1 1 b a x y 0 0 0 0 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 b a x b 1 0 0 1 1 2 0 1 0 1 4 1 0 0 1 b <= (not b and not a and x) or (not b and a and not x) or (b and not a and not x) b a x a 2 0 1 0 1 3 0 1 1 1 5 1 0 1 1 7 1 1 1 1 b a x a Gruppe 1: 2 0 1 0 1 Gruppe 2: 3 0 1 1 1 5 1 0 1 1 Gruppe 3: 7 1 1 1 1 2:3 0 1 - 3:7 - 1 1 5:7 1 - 1 a <= (not b and a) or (a and x) or (b and x) b a x y Gruppe 0: 0 0 0 0 1 Gruppe 1: 4 1 0 0 1 Gruppe 2: 5 1 0 1 1 6 1 1 0 1 Gruppe 3: 7 1 1 1 1 0:2 - 0 0 4:5 1 0 - 4:6 1 - 0 5:7 1 - 1 6:7 1 1 - 0:2 - 0 0 4:5 1 0 - 6:7 1 1 - 4:6 1 - 0 5:7 1 - 1 0:2 - 0 0 4:5:6:7 1 - - 4:6:5:7 1 - - y <= (not a and not x) or (b) b <= (not b and not a and x) or (not b and a and not x) or (b and not a and not x) a <= (not b and a) or (a and x) or (b and x) y <= (not a and not x) or (b)
entity meinuebergangsschaltnetz is port ( b, a: inout bit; x: in bit ); end; entity meinausgangsschaltnetz is port ( b, a: out bit; y: out bit ); end; architecture verhalten of meinuebergangsschaltnetz is begin b <= (not b and not a and x) or (not b and a and not x) or (b and not a and not x); a <= (not b and a) or (a and x) or (b and x); end; architecture verhalten of meinausgangsschaltnetz is begin y <= (not a and not x) or (b); end;